1 Bit - Springer Nature

A Low-Area Low-Power Column-parallel Digital Decimation Filter Using 1-Bit Pre-BWI Topology for CMOS Image Sensor in 40-nm CMOS Process

In this paper, a low-area and low-power configuration of a second-order digital decimation filter with 13-bit dynamic range is suggested for column-parallel ADC array in a CMOS image sensor. The proposed structure shifts the location of the bit-wise-inversion cell to the front of the ripple counter and subtracts a predetermined array-wise residual value set by the ADC oversampling ratio. Without altering the overall logical functionality of the digital decimation filter, the number of inverters and multiplexers in the BWI unit has dramatically reduced. In Then, the number of inverters and multiplexers in the BWI unit has dramatically decreased.

Source link: https://doi.org/10.1007/s00034-021-01898-0

* Please keep in mind that all text is summarized by machine, we do not bear any responsibility, and you should always check original source before taking any actions